1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a flash memory.
2. Description of Related Art
Flash memory is a memory device that allows multiple data reading, writing and erasing operations. In addition, the stored data will be retained even after power to the device is turned off. With these advantages, it has been broadly applied in personal computer and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon. The control gate is set up above the floating gate with an inter-gate dielectric layer separating the two. Furthermore, a tunneling oxide layer is also set up between the floating gate and an underlying substrate (the so-called stack gate flash memory). Electric charges are injected into or drained away from the floating gate by the application of a positive or negative voltage at the control gate. The presence or absence of electric charges inside the floating gate indicates the state of a data storage unit.
FIGS. 1A to 1D are schematic cross-sectional views showing the progression of steps for producing a conventional flash memory device. The substrate 100 in FIGS. 1A to 1D is partitioned into two major regions, a memory cell region 102 and a peripheral circuit region 104.
First, a tunnel dielectric layer 106 is formed over the memory cell region 102 and a liner layer 108 is formed over the peripheral circuit region 104 as shown in FIG. 1A. Thereafter, a conductive layer 110 is formed over the entire substrate 100. The conductive layer 110 over the memory cell region 102 is patterned to form a linear array of conductive layers 110a. An inter-gate dielectric layer 112 is formed over the substrate 100. The inter-gate dielectric layer 112 comprises an oxide/nitride/oxide composite layer, for example.
As shown in FIG. 1B, a patterned photoresist layer 114 is formed over the substrate 100. The patterned photoresist layer 114 covers the memory cell region 102 but exposes the peripheral circuit region 104. Using the patterned photoresist layer 114 as a mask, the inter-gate dielectric layer 112, the conductive layer 110 and the liner layer 108 on the peripheral circuit region 104 are removed. Thereafter, a gate dielectric layer 116 is formed over the peripheral circuit region 104.
As shown in FIG. 1C, the patterned photoresist layer 114 is removed. A conductive layer 118 is formed over the substrate 100.
As shown in FIG. 1D, the conductive layer 118 is patterned to form a control gate conductive layer 118a over the memory cell region 102. Thereafter, the inter-gate dielectric layer 112, the conductive layer 110a and the tunnel dielectric layer 106 are patterned to form a stack gate structure comprising of the control gate conductive layer 118a, the inter-gate dielectric layer 112a, the conductive layer 110b and the tunnel dielectric layer 106a. In the meantime, the conductive layer 118 on the peripheral circuit region 104 is patterned to form a gate structure comprising of a gate oxide layer 116a and a conductive layer 118b. 
In the aforementioned fabrication process, the inter-gate dielectric layer 112 is a thin and brittle film and hence can be easily damaged in an ashing process and a cleaning process after patterning the photoresist layer 114. When the inter-gate dielectric layer 112 is defective, the capacity to retain data inside the flash memory will deteriorate.
On the other hand, if a weaker cleaning agent is deployed to remove the photoresist layer so that any damage to the uppermost oxidation layer of the inter-gate dielectric layer 112 is minimal, some polymer residue from the photoresist material may still cling to the original substrate and lead to a metallic contamination of the gate layer.